Clock Gating Check

Clock gating occurrences are any signals on the clock path that block (gate) the clock from propagating.
• The enable path of the clock gate must arrive enough time before the clock itself to ensure glitch-free functionality (and similarly hold after the edge).

source

---

---

Similar Snippets

---

Clock Gating Check - vlsi

Difference Between Clock Buffer And Normal Buffer - vlsi

Synopsys Pocv Setup Commands - vlsi

Sta Multi Mode Multi Corner - vlsi

Synopsys Primetime Commands - vlsi