Clock buffer have equal rise time and fall time, therefore pulse width violation is avoided.
In clock buffers Beta ratio is adjusted such that rise & fall time are matched. This may increase size of clock buffer compared to normal buffer.
Normal buffers may not have equal rise and fall time.
Clock buffers are usually designed such that an input signal with 50% duty cycle produces an output with 50% duty cycle. Main reason for this practice is existing Half-cycle paths. If you have Rise to Fall edge or fall to rise edge paths, duty cycle needs to be close to 50 percentage. As lesser the duty cycle, lesser that time available for that data to flow from one register to other.
Clock net is one of the High Fanout Net(HFN)s. The clock buffers are designed with some special property like high drive strength and less delay. Clock buffers have equal rise and fall time. This prevents duty cycle of clock signal from changing when it passes through a chain of clock buffers.