Latch Based Clocking
• Every cycle is broken by two latches
- That means that each signal must go through two latches
- So if you set clocks up correctly, hold time should not be bad
• Problem is each latch has a different clock, so skew can cause
hold time issues
• But in this system there are no hard edges
- Transparency window of each latch is large, ½ a clock cycle
• The large transparency window means
- Can borrow time naturally
• Can have up to 1.5 cycle (if there was no skew) in some cycle, if the adjacent cycle only needs .5 w/o skewing clocks
- Is insensitive to clock skew; for critical paths, data sets timing
Clock Tree Structure Types - vlsi
On Chip Variation Analysis - vlsi
Difference Between Clock Buffer And Normal Buffer - vlsi
Synopsys Primetime Commands - vlsi
Synopsys Pocv Setup Commands - vlsi