Causes of timing variations can include small variations in the way that features defined on a mask print on the surface of the chip because of the effect of surrounding features, variations in processes such as doping levels or etching that may remove more or less of a critical feature such as a gate stack or polysilicon interconnect. Even activity has an impact through factors such as IR drop, which became more prominent in design as voltages approached, and passed, the 1V level.
In the past, OCV affects has been taken in to account by applying a general margin across the entire chip. This has resulted in the pessimistic timing analysis. To remove the pessimism, two new approaches have been used.
Below is one example for AOCV table:
object_type : lib_cell
rf_type : rise
delay_type : cell
derate_type : late
path_type : data
object_spec : 10nmlib/BUF_X4
depth : 1 2 3 4 5 6 7 8 9 10
table: 1.183 1.145 1.122 1.109 1.0901 1.0801 1.0736 1.0650 l.0601 1.055
In POCV, instead of applying a specific derating factor to a cell, cell delay is calculated based on a delay variation of that cell. This delay variation (σ ) for each cell is obtained through Monte-Carlo HSPICE simulation. The variation value σ is a unique value specific to that library cell.
This means that a given path doesn’t have to be analyzed stage-by-stage; the number of stages can be counted, with the basic stage delay mean and sigma then used to calculate the path delay and accumulated variation.
In POCV timing analysis, instead of specifying absolute minimum and maximum delays for each timing arc, the tool calculates the delay for each arc as a function of the Gaussian or normal distribution. By default the tool calculates the slack at 3 standard deviations below the nominal slack. The standard deviation multiplier can be changed in the primetime.